DDR Design Guidelines:

What You Need to Know to Achieve First Pass Success

Each time a new generation of DDR is released, its’ performance capabilities are almost 2x superior than the previous generation. These technological advancements mean more difficult design requirements and tighter tolerances for PCB designers to navigate. Join us to learn how to overcome common challenges and helpful design techniques when incorporating DDR4 into your next design.

What you will learn:

  • DDR4 overview and structure
  • Common challenges when incorporating DDR into your design
  • Electrical and layout techniques to address the challenges
  • Defining and meeting constraint requirements
  • Verifying proper interface operation
  • What’s to come with DDR5
DDR Design Guidelines
April 2nd 2:00 - 3:00pm EDT

About your Presenter's

Jerry Long

Product and Senior Applications Engineer

Jerry is a Senior Applications Engineer for EMA Design Automation. Jerry provides high-end customer support for several Cadence products, as well as product development and technical marketing guidance for the TimingDesigner product. With a bachelor’s degree in electrical engineering from the University of Texas at Austin, Jerry has been involved in several product lines involving verification and timing analysis.

Orlen Bates

Field Applications Engineer

Orlen Bates is a Sr. Field Applications Engineer and has been in the field of PCB design for 43 years and has been with EMA for over 16 years. Orlen attended Vocational Tech School, earning a degree in Drafting & Design Technologies. With many years of printed circuit, wire board design, and DFM knowledge, Orlen is a highly skilled professional in the field of engineering design. 

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